1. Field of the Invention
The present invention relates to a semiconductor devices and more particularly, to element isolation in a heterojunction bipolar transistor using III-V compound semiconductor such as gallium arsenic (GaAs).
2. Description of the Related Art
A heterojunction bipolar transistor (HBT) has very promising prospects as a transistor for use in a microwave circuit and a high-speed logical circuit because of its excellent performances in high frequency and switching operations compared with silicon bipolar transistors.
An HBT using GaAs, in particular, is being developed as a superhigh speed device for the next generation.
In order to realize a high-speed and low-power consumption transistor, miniaturing techniques are required. However, the miniaturizing techniques have big problems, which must be solved in future.
For example, an Al.sub.x Ga.sub.1-x As/GaAs heterjunction bipolar transistor comprises a wafer as shown in FIG. 12. The wafer is formed by epitaxially growing an n.sup.- type GaAs layer as a collector layer 102, a p.sup.+ type GaAs layer as a base layer 103, and an n type Al.sub.x Ga.sub.1-x As layer as an emitter layer 104 sequentially on an insulating GaAs substrate 101 with the use of a molecular beam epitaxy (MBE) technique, a metal organic chemical vapor deposition (MOCVD) technique or the like techniques.
The wafer thus formed is then subjected to a mesa etching to expose the collector layer 102 and the base layer 103. Subsequently, a collector electrode 105, a base electrode 106 and an emitter electrode 107 are formed thereon, and protons or boron are implanted to thereby form an element isolation region 108 having a high resistance as shown in FIG. 13.
A heterojunction bipolar transistor thus prepared is shown by a plan view in FIG. 14. In the connection of the transistor to other elements or pads located outside the transistor, the base and collector electrodes 106 and 105 can be led directly onto the element isolation region 108 of a semi-insulated high-resistance layer. Therefore, these electrodes can be easily connected to other outside elements. On the other hand, when the emitter electrode 107 is to be led out outwards in the same manner, it is short-circuited with the p type GaAs layer surrounding the mesa portion of the emitter.
For the purpose of avoiding the short circuit, the surface of the emitter electrode 107 is coated with an insulating film such as a silicon oxide film, a contact hole H is provided on the emitter electrode 107, and a leading wire 109 is formed through the contact hole as shown in FIG. 15.
However, this structure requires space for the contact hole and allowance for positioning with respect to the contact hole in the emitter electrode 107, which unfavorably impedes the miniaturization of the device.
For eliminating this problem, it has been exercised that the top surface of the emitter mesa is also subjected to the implantation of proton or boron ions so as to form a high resistance top surface, and the side surface of the emitter region 104 is made contacted with the high-resistance region as shown in FIG. 16. With this structure, the emitter electrode 109 can be lead out outside of the emitter region 104 without requiring any contact hole and the device can be miniaturized because the area of the emitter electrode can be reduced without space for contact hole and allowance for the positioning of the contact hole.
The above-described method for providing a high resistance on the top of the emitter mesa by the implantation of proton or boron ions therein is effective in simplifying the miniaturizing process. This method, however, has a problem that, since crystalline defects introduced by the ion implantation are directly contacted with the interface of the emitter-base junction, an electric current created by the generation and recombination is increased in the interface region, whereby the current gain of the transistor is decreased.
Referring to FIG. 17 which is a cross-sectional view taken along line A--A in FIG. 16, recombination centers (shown by marks x in FIG. 17) are induced by the ion implantation in the junction between the p type GaAs layer of the base layer 103 and the n type Al.sub.x Ga.sub.1-x As layer of the emitter layer 104, and electrons injected through the emitter are recombined in the recombination centers.
Table 1 shows leak currents on the mesa isolation end surface and ion implantation isolation end surface when the base-emitter voltage is applied such that the collector current density becomes 10.sup.4 A/cm.sup.2 in the heterojunction bipolar transistor.
TABLE 1 ______________________________________ Mesa isolation type: 0.1 uA/um Ion implantation isolation type: 30 uA/um ______________________________________
As shown in Table 1, the leak current on the mesa isolation end face is 0.1 uA/.mu.m whereas the leak current on the ion implantation end face is 30 uA/.mu.m, which is 300 times of that flowing on the mesa isolation end face. The leak current on the mesa isolation end face is mainly the surface recombination current.
Assuming that in FIG. 16, emitter length is the length of the mesa isolation end face and emitter width is the length of the ion implantation isolation end face, FIG. 18 shows the current gain of the transistor when the emitter length of the transistor is varied with the emitter width W being 2 .mu.m. It will be seen from FIG. 18 that as the emitter length is decreased, the influence of the recombination current on the ion implantation isolation end face becomes greater and thus the current gain of the transistor is decreased. Accordingly, it is practically impossible to reduce the emitter length, which impedes the miniaturization of the device.
As discussed above, providing a high resistance to the emitter/base end face for isolation by the ion implantation in the heterojunction bipolar transistor has a problem that, as the emitter length is decreased, the influence of the recombination current on the ion implantation isolation end face is increased and the current gain of the transistor is decreased.